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XOCLCC6EVB
LVDS : Driver termination is a 100 W resistor across the
differential lines located at the receiver input.
Step 3: Configure FSEL and OE
The FSEL and OE control pins can be controlled from an
external source via the appropriate test point, or via the
Table 4. TYPICAL LAB SETUP
LOGIC Levels Power Supply
Typical Lab
Setup
jumper headers located on the evaluation board, as indicated
in Figures 2 and 7. Refer to the specific device datasheet for
details on the proper settings for these pins.
LVPECL
CML
LVDS
Split 3.3 V
Single ? 3.3 V
Single 3.3 V
See Figure 4
See Figure 5
See Figure 6
+2.0V
Digital Oscilloscope
Or Frequency Counter
VDD = +2.0V
H
L
VDD
+
+2.0V
?
OE
J1
Power Supply
H
L
50 W
+
FSEL
J2
+1.3V
?
SMAGND
C3
50 W
DUTGND
C4
VEE = ? 1.3
? 1.3
0V
Figure 4. Split Power Supply Lab Setup for LVPECL Outputs (DO NOT JUMPER DUTGND and SMAGND)
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